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ATmega128
W riting this bit to one enables the USARTn Transmitter. The Transmitter will override normal
port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn
to zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and transmit buffer register do not contain data to be transmit-
ted. W hen disabled, the transmitter will no longer override the TxDn port.
? Bit 2 – UCSZn2: Character Size
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(character size) in a frame the Receiver and Transmitter use.
? Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames with 9-
data bits. Must be read before reading the low bits from UDRn.
? Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the 9th data bit in the character to be transmitted when operating with serial frames
with 9 data bits. Must be written before writing the low bits to UDRn.
USART Control and
Status Register C –
Bit
7
6
5
4
3
2
1
0
UCSRnC
Read/ W rite
Initial Value
–
R/ W
0
UMSELn
R/ W
0
UPMn1
R/ W
0
UPMn0
R/ W
0
USBSn
R/ W
0
UCSZn1
R/ W
1
UCSZn0
R/ W
1
UCPOLn
R/ W
0
UCSRnC
Note that this register is not available in ATmega103 compatibility mode.
? Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, these bit must be written
to zero when UCSRnC is written.
? Bit 6 – UMSELn: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 77. UMSELn Bit Settings
UMSELn
0
1
Mode
Asynchronous Operation
Synchronous Operation
? Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.
If a mismatch is detected, the UPEn flag in UCSRnA will be set.
Table 78. UPMn Bits Settings
UPMn1
0
0
1
1
UPMn0
0
1
0
1
Parity Mode
Disabled
(Reserved)
Enabled, Even Parity
Enabled, Odd Parity
190
2467X–AVR–06/11
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